Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemes

ABSTRACT

A transistor integration process provides a damascene method for the formation of gate electrodes and gate dielectric layers. An interlayer-dielectric film is deposited prior to the gate electrode formation to avoid the demanding gap fill requirements presented by adjacent gates. A trench is formed in the interlayer-dielectric film followed by the deposition of the gate material in the trench. This process avoids the potential for damage to high-k gate dielectric layers caused by high thermal cycles and also reduces or eliminates the problematic formation of voids in the dielectric layers filling the gaps between adjacent gates.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods for forming semiconductortransistors. More particularly, the present invention relates to methodsfor integrating high-k gate dielectric layers and gate electrodes in thetransistor formation process.

2. Description of the Related Art

Designers and semiconductor device manufacturers constantly strive todevelop smaller devices from wafers, recognizing that circuits withsmaller features generally produce greater speeds and increased packingdensity, therefore increased net die per wafer (numbers of usable chipsproduced from a standard semiconductor wafer). To meet theserequirements, semiconductor manufacturers have been forced to build newfabrication lines at the next generation process node (gate length).

However, with smaller devices several new problems have surfaced. Forexample, in the manufacture of Very Large Scale Integrated (VLSI)ultra-submicron technologies, the small technology node sizes requireultra high-k dielectric layers as well as very small gate-to-gatespacing. These structural requirements have in turn created problemspreventing full implementation of these process technologies. Forexample, high-k gate dielectrics are sensitive to the high thermalcycles typically required to activate dopants and repair the damage fromimplantation steps. In addition, the ultra small spacing between gateelectrodes requires heightened efforts in avoiding void formation duringthe transistor interlayer deposition.

With smaller spaces between adjacent gates, the gap-filing challengesincrease dramatically. These challenges result from the tendency ofdielectrics formed on a structure having at least one steep sidewall toproduce voids from the effect of an overhang. That is, as a dielectriclayer such as a primary layer dielectric (PMD) or other interlayerdielectric (ILD) is deposited, given a trench having a large enoughaspect ratio, i.e., the height of the trench divided by the width, voidswill tend to appear in the deposited dielectric layer. Typically, anoverhang will be created at the one of the upper corners of thestructure defining the trench.

At some point during the process of depositing the dielectric layer, thedielectric at the level of the overhang thickness from opposing sides ofthe trench will meet, thus in some cases encapsulating a void in thedielectric. As the spacing between adjacent gates decreases with thedecrease in dimensions of the process technology nodes, the adjacentgates will present a trench structure to the interlayer dielectric filmwhen it is deposited.

Much effort in process engineering is required to tune the process toavoid the formation of the void. Preventing void formation typicallyinvolves selecting the process parameters to control the overhangthickness relative to the dielectric thickness at the bottom of thesidewall of the trench and controlling the trench width. But thelatitude available to the designer to alter the process parameters orthe trench dimensions to mitigate void formation problems decreases asprocess technology nodes decrease in size.

Accordingly, what is needed is an improved process for forming ultrasmall transistors, one that overcomes the low thermal budgets of theconventional process and its tendencies to produce voids betweenadjacent gate electrodes.

SUMMARY OF THE INVENTION

To achieve the foregoing, the present invention provides transistorintegration schemes that avoid the potential damage to high-k gatedielectric layers caused by high thermal cycles and also reduces oreliminates the problematic formation of voids in the dielectric layersfilling the gaps between adjacent gates. The novel integration schemedeposits an interlayer-dielectric film prior to the gate electrodeformation to avoid the demanding gap fill requirements presented byadjacent gates. A trench is formed in the ILD followed by the formationof the gate dielectric and gate electrode in the trench. Thus, the gateis formed by a damascene method.

A second ILD layer is formed after formation of the gate electrode toprotect the gate electrodes during a chemical mechanical polishing stepdirected to the formation of contacts. By forming the gate electrode bythe damascene method described, the first ILD layer is used in lieu of aspacer to surround the gate electrode. This allows greater flexibilityin choosing the first ILD layer to be a different material than thesecond ILD layer.

Moreover, forming the gate electrode in the etched trench allows greaterflexibility in choosing the gate conductor material. Patterning the gateelectrode by an additive process frees up the gate electrode to beformed from a material not limited by the etching chemistry constraintsof the gate electrode and adjacent layers.

According to one embodiment of the present invention, a method offorming a transistor gate electrode is provided. A dielectric layer isformed directly on a semiconductor substrate, the substrate having animplanted source and drain region. A trench is then formed in thedielectric layer. A conformal second dielectric layer is deposited toline the trench, thus forming a gate dielectric. A gate conductormaterial is then deposited to fill the trench.

According to another embodiment, a method of forming an integratedcircuit transistor is provided. Source and drain regions for thetransistor are defined in the substrate prior to the formation of thegate electrode. After the source and drain regions are defined, adielectric layer is formed on the substrate and patterned to form atrench. First, a high-k dielectric film is disposed in the trench toline the trench. Then, a gate conductive layer is formed by filling inthe trench, the gate conductive layer being configured to form a gateelectrode for controlling current flow between the source and drainregions. Formation of the gate electrode is completed by chemicalmechanical polishing.

According to another embodiment, a method of forming an integratedcircuit transistor is provided. Source and drain regions for thetransistor are defined in the substrate prior to the formation of thegate electrode. After the source and drain regions are defined, adielectric layer is formed on the substrate and patterned and etched toform a trench. Etching of the trench continues until a channel region isetched in the substrate. The channel region is then filled with achannel material, preferably by epitaxial growth. This scheme allows forcontrol of the channel characteristics using silicon or silicongermanium. Next, a high-k dielectric film is disposed in the trench toline the trench. Then, a gate conductive layer is formed by filling inthe trench, the gate conductive layer configured to form a gateelectrode for controlling current flow between the source and drainregions. Chemical mechanical polishing completes formation of the gateelectrode.

These and other features and advantages of the present invention aredescribed below with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1O are diagrams illustrating a method of forming asemiconductor integrated circuit in accordance with one embodiment ofthe present invention.

FIG. 2A-2G are diagrams illustrating a method of forming a semiconductorintegrated circuit in accordance with an alternative embodiment of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference will now be made in detail to preferred embodiments of theinvention. Examples of the preferred embodiments are illustrated in theaccompanying drawings. While the invention will be described inconjunction with these preferred embodiments, it will be understood thatit is not intended to limit the invention to such preferred embodiments.On the contrary, it is intended to cover alternatives, modifications,and equivalents as may be included within the spirit and scope of theinvention as defined by the appended claims. In the followingdescription, numerous specific details are set forth in order to providea thorough understanding of the present invention. The present inventionmay be practiced without some or all of these specific details. In otherinstances, well known process operations have not been described indetail in order not to unnecessarily obscure the present invention.

FIGS. 1A-1O are diagrams illustrating a method of forming asemiconductor integrated circuit in accordance with one embodiment ofthe present invention. It should be noted that in each sequence ofdrawings provided herein, reference numbers identified earlier in thesequence apply to those same elements in other drawings of the sequenceunless otherwise noted or the context otherwise dictates.

The process begins as illustrated in FIG. 1A with an isolation trench104 or other isolation structure formed on a semiconductor substrate102. Isolation trenches may be formed by conventional steps, well knowto those of skill in the relevant art. For example, a conventionalshallow trench isolation typically involves depositing an oxide layer onthe surface of a semiconductor substrate, followed by deposition orformation of a nitride layer that is patterned to act as a mask forshallow trench etch. The nitride mask also has a role as a properin-situ control layer for CMP, and preventing further oxidation of thesubstrate surface where it is masked. The next step involves etching ofthe shallow trench followed by formation of an oxide liner in theshallow trench. Following trench formation, the trenches are typicallycleaned using combinations of conventional dry and wet chemistry and thetrench side walls oxidized to form a liner, typically a few hundredAngstroms thick, to repair any damage caused by the plasma used inetching the trench. This oxide liner also provides a base for thesubsequent insulation deposition.

Following formation of the oxide liner, the trench is filled withdeposited oxide. For example, the trench may be filled with a silicondioxide layer, deposited by chemical vapor deposition (CVD),high-density plasma (HDP) deposition, or spin-on glass (SOG), on theintegrated circuit substrate 102. The partially formed device is thensubjected to chemical mechanical polishing (CMP) and planarized down toa top surface comprising the top of the trench 104 and to the top of thesubstrate layer 102 adjacent to the trench 104. The isolation regionsare important for electrically isolating active areas formed in thesubstrate 102 from each other.

As shown in FIG. 1A, after the insulating layer, i.e., the trench oxide,is polished using chemical mechanical polishing means, the nitride layerstripped and the oxide residue removed using an HF cleaning step, thesurface 108 of the insulating layer at the top of the trenches 104 issubstantially planar. After the isolation structures shown in FIG. 1Aare formed, the fabrication process proceeds to forming features ofactive areas, e.g., transistor devices.

In complementary MOS (CMOS) technology, an NMOS transistor and a PMOStransistor are fabricated adjacent to each other on the same substrate,which may initially be lightly doped or undoped. Circuits made from CMOSdevices require less power and generate less heat than equivalentcircuits designed with NMOS or PMOS devices alone. This embodiment ofthe present invention illustrates the transistor formation process asimplemented in a CMOS device. It should be appreciated, however, thatthe scope of the present invention is not so limited. That is, thetechniques described herein are applicable to the formation of gates andgate dielectric layers in any transistors utilizing these features,including the full variety of MOS field effect transistors, such as PMOSand NMOS transistors.

In order to form the CMOS transistor, first and second wells of n typeand p type, respectively, are formed in the substrate by conventionalprocess steps. That is, one or more PMOS transistors are formed in the ntype well, and one or more NMOS transistors are formed in the p typewell. PMOS and NMOS transistors are paired together to create the CMOSdevice having the advantages described above, further including very lowstandby current consumption.

The device formation proceeds with the well formation, as illustrated inFIG. 1B. In specific, the transistor integration process of the firstembodiment continues by next implanting the p- and n-wells using n-welland p-well masks on the corresponding sides of the isolation trench. Therespective wells are formed by conventional doping methods well known tothose of skill in the art. For example, the n-well mask formation isfollowed by an n-well implant to form the n-well region 114 in the areaof the substrate exposed under the n-well mask (not shown). Suitablen-type dopants used for formation of the well include phosphorus. Inorder to repair the damage from the ion implantation, an n-well annealstep preferably follows the implantation, as is done typically followingthe conventional well formation steps. In turn, a p-well mask is formedon the wafer, followed by a p-well implant into the areas exposed by themask, i.e., into the p-well region 112. The respective wells may beformed using conventional dopants. The most commonly used dopant speciesfor p- and n-wells are boron and phosphorus, respectively. The p-welland n-well dopings form a p-n junction 110 under the field oxide ofadjacent n+ and p+ diffusion regions 114 and 112. It is important forthe device operation that these two diffusion regions (devices) areclearly electrically separated. A p-well anneal step follows. Since thepost well anneal steps are well known to those of skill in the relevantart, further description is deemed unnecessary here.

Next, as illustrated in FIG. 1C, the lightly doped drain (LDD) regionsare formed in the respective wells. These are also known as lightlydoped diffusions. In this step and many of the other steps of theembodiments of the invention, the n-type doping is described asoccurring prior to the p-type doping. It will be appreciated by those ofskill in the relevant arts that the order of the n-type and p-typedoping can be interchanged without adversely affecting the formeddevice. Thus the scope of the present invention is intended to includethe respective p-type and n-type doping without limitation to theparticular order of the dopants for a particular step in the process.Hence, the p-type dopants can alternatively be introduced into then-well to form the p-LDD regions before formation of the n-LDD regionsin the p-well.

The embodiments of the present invention form drain engineering prior tothe formation of the gate electrode. In particular, the lightly dopeddrain implants as well as punch through stop layer and source and draindefinition all occur prior to the building of the building of the gateelectrode. Although these implants are not self-aligned, they providesubstantial advantages in thermal cycle engineering. That is, masking isused in formation of the LDD, punch through, and source/drain definitionimplants. In particular, for each well, a first well mask is used forformation of a subsequent LDD and punch through implant for that well.After these regions are formed in each well, a separate source/drainmask is used for each well in order to form the more heavily dopedsource and drain regions. As well known to those of skill in the art,LDD regions are used to protect against hot electron effects whereaspunch through implants protect against breakdown mechanism caused by theoverlap between the source and drain depletion regions.

The drain engineering commences with the LDD implant, as illustrated inFIG. 1C. The scope of the invention is intended to extend to any of theconventional techniques for implanting lightly doped diffusions, punchthrough implants, and source or drain regions. Preferably, ion implantprocedures are used to implant the respective portions of the substrateto create these diffusion regions in the substrate 102. Initially, ap-well mask is formed to cover the n-well 114 and to expose portions ofthe p-well 112. Next, a lightly doped drain implant occurs. Preferably,the LDD implant 120 of n-type dopants (into the p-well 112) includesn-type dopant ions in a suitable concentration in accordance with theprocess technology node dimensions and the particular type of dopantsused. These dopants and concentrations are expected to conform to thoseused in conventional process steps and adjusted in accordance with thedesired depth of the implant, the type of dopant, and the presence orabsence of overlying sacrificial layers. For example, without intendingto be limiting, a suitable n-type dopant implantation at the 0.18 microntechnology node involves a dosage range of 1 to 10×10¹³ cm⁻² ofphosphorus ions.

After formation of the LDD implant 120 in the p-well 102, a punchthrough stop implant 122 is formed. Suitable concentrations of dopantsare known to those of skill in the art and therefore will not bedescribed in complete detail here. A suitable n-type punch through stopimplant at the same technology node could use phosphorus ions or anyother n-type ion at any appropriate dosage determined by methods knownto those of skill in the art. The depth of the punch through stopimplant is controlled such that the punch through implant region isburied in the substrate 102 at a predetermined depth in accordance withconventional techniques.

Next, annealing occurs to repair the damage to the crystalline structurefrom the n-type implant and to activate the dopants. Annealing of theLDD and punch through regions preferably occurs in conformance withconventional techniques known to those of skill in the relevant art.Further details are deemed unnecessary here. As noted above, annealingtakes place at very high temperatures, e.g., 1000 to 1200 degrees C.Performing the annealing before the formation of the gate and gatedielectrics allows for the control of the thermal budget during thehigh-k dielectric formation and subsequent gate electrode processingthat may include the use of low melting point temperatures (e.g.,Tungsten).

Following formation of the LDD and punch through implants in the p-well112, the process proceeds to form similar implants in the n-well 114.That is, using an n-well mask, a p-type LDD implant 116 and p-type punchthrough implant 118 are formed in the n-well 114. Suitableconcentrations of dopants are known to those of skill in the art andtherefore will not be described in complete detail here. Typicallyanother anneal is not necessary, since the high-k thermal processing maybe used to activate the P-type dopants.

Next, the source and drain regions are defined for each transistor.First, as illustrated in FIG. 1D, the formation of a p source-drain mask124 is then followed with a p-type source-drain implant 126 into then-well 114. Following the p-type source drain implant 126, the nsource-drain mask 128 is formed to expose the appropriate region for then-type source drain implant 130. That is, the n-type source-drainimplant 130 is formed in the p-well 112 as specifically illustrated inFIG. 1E. The n-type source-drain mask 128 is patterned such that theportion of the substrate positioned under the predetermined location forthe gate of the NMOS transistor is protected by the mask 128. Suitabledopants for implantation into the n-well source and drain regions areknown to those of skill in the relevant arts and thus furtherdescription here is deemed unnecessary.

It will be appreciated that further annealing is required to restore thesubstrate silicon structure after the source drain implant. Preferably,the annealing of this region occurs during the high temperaturesprovided during the high-k gate dielectric layer deposition.Alternatively, a separate anneal step may be performed after formationof both of the source and drain regions in both of the p-wells andn-wells.

The present invention embodiments described rely on the deposition of adielectric material on the substrate to form the gate by an additivedamascene process. In particular, and as illustrated in FIG. 1F, aninter-layer dielectric (ILD) layer 132 is preferably deposited to athickness in the range of 1000 to 3000 Angstroms, more preferably 1600to 2500 Angstroms. Although these ranges are preferable, the inventionscope is not so limited. The thickness of the deposited ILD layer 132may be selected to whatever thickness is deemed suitable inconsideration of the design and materials used for the dielectric.Preferably, the dielectric layer comprises one of undoped silicate glass(USG) or phospho-silicate glass (PSG). Although the inventive processhas been described for illustration purposes as including PSG or USG,the invention is not so limited. The scope of the invention is intendedto extend to any dielectric material that can be suitably deposited orformed and etched to form a trench. That is, any dielectric layer thatcan be deposited on the substrate and patterned and etched to form gateelectrode trenches. In other words, as long as the dielectric materialexhibits suitable selectivity to the etchant chemical used for formingthe trench and, within a broad range of suitable electricalcharacteristics, it may be used for forming the trench.

Next, as illustrated in FIG. 1G, the dielectric (ILD) layer 132 ispatterned by conventional photolithography, using a patterned resistlayer to etch the ILD layer 132. The ILD layer is etched to form anelectrode trench 134 at the locations specified for the transistorgates. These materials have been conventionally used for formingpre-metal dielectrics (PMD's). As known to those of skill in therelevant arts, PSG provides several advantages including an ability toreadily reflow.

The etching of the gate electrode trench 134 is preferably performedusing a fluorine based anisotropic dry etch, for example, either C₂F₆ orCF₄. Etching of the ILD layer 132 to form the gate electrode trench 134may be performed using etching chemicals and techniques suitable forconventional contact hole etches. Etching preferably is performed to adepth that exposes the substrate 102. The width of the trench isdependent upon the particular process node involved in the fabrication.

Next, as illustrated in FIG. 1H, the gate dielectric formation processcommences. Initially, a relatively thin high-k dielectric layer 136 isdeposited. Many suitable high-k layers are known in the art to includezirconium oxides and multi layered laminates. Preferably, the thicknessof the high-k layer could be any thickness and still fall within thescope of the invention. It should be understood that as with theconventional process, the thickness of the high-k dielectric layer isdependant on the desired electrical characteristics for the device andthe characteristics of the dielectric gate material, specificallyincluding the permittivity k of the gate dielectric material. Bydepositing the dielectric film in this damascene manner, the thicknessof the high-k layer is well controlled. Further, by depositing the highk gate dielectric layer and the subsequently formed gate afterimplantation of the source and drain regions, the thermal budget for thedevice can be increased. In other words, using the described fabricationsequence of this embodiment, neither the high-k dielectric layer nor thegate conductor are in place during the high temperatures required toanneal the source, drain and other implants.

Next, as illustrated in FIG. 1I, a gate electrode conductive material138 is deposited to fill the trench 132 and to create an overburdenregion. The gate electrode conductive material 138 can comprise anyconductive material such as including but not limited to Cu, W, and Al.Doped polysilicon may be used for the gate electrode as well. The dopedpoly gates are used in the conventional transistor fabrication steps inpart due to their low surface state densities that makes them suitablefor exposure to the high temperatures present during annealing. Becauseneither the gate electrode not the high-k gate dielectric layer arepresent during annealing, the range of conductive materials used for thegate electrode in the described embodiments of the present invention aremuch greater. For example, aluminum oxidizes readily during annealingconditions but can readily be used in the presently described processsince the formation of the gate conductive layer occurs after theannealing steps.

After deposition of the gate electrode layer 138, chemical mechanicalpolishing is preferably performed to remove the overburden region andthus to planarize the gate electrode 138 to be coplanar with the topsurface of the dielectric layer 132. The partially formed device aftercompletion of the planarization step is illustrated in FIG. 1J.

In order to form contacts for electrical connection to the device, asecond ILD deposition step then follows, as shown in FIG. 1K. The secondILD layer 140 may comprise any suitable dielectric layer such as anoxide and also may comprise the same constituency as the first ILD layer132. Preferably, the second ILD layer 140 has a thickness in a range onthe order of 5000 Angstroms. However, the dimensions of the second ILDlayer 140 are process dependent. The second ILD layer 140 may be formedby conventional techniques known to those of skill in the art includingchemical vapor deposition (CVD) methods. The second ILD layer isdeposited after the gate electrode is formed to protect the gateelectrode during the contact conductor chemical mechanical polish step.The use of a second ILD layer for contact formation and CMP protectionallows flexibility in choosing the first ILD material. For example,nitrides are not conventionally used in forming the dielectricsurrounding the gate electrode (e.g., the pre-metal dielectric) due totheir tendencies to damage the surface of the substrate. By forming asecond ILD layer on top of the first, the substrate can be protectedfrom a nitride or other similar dielectric present in the second ILDlayer, yet providing the passivation advantages of the nitridecontaining second ILD.

Next, as illustrated in FIG. 1L, the second ILD layer 140 is etched toform contact holes 142 and gate contact holes 144. Typical diameters forthese holes range from 0.14 to 0.25 microns, but again, the sizes areprocess technology node dependent. Conventional etching chemicals andtechniques for forming the contact holes can be used to form the holesfor the contacts and gate contacts. Accordingly, further details aredeemed unnecessary here.

Next, as further illustrated in FIG. 1M, salicide layers 146 are formedat the bottom of the contact holes 142 and on top of the gate electrode144. Salicides may preferably be formed by CVD, atomic layer deposition(ALD), or plasma enhanced chemical vapor deposition (PECVD) means toflow into and suitably fill the contact holes. CVD processes used indepositing and forming cobalt or nickel salicides are known in therelevant arts and thus further details are deemed unnecessary here. Inparticular, the CVD process may be appropriately adjusted to suit thedeposition of salicide materials in the bottom portions of contact holesand other high aspect ratio apertures. As known in the relevant arts,salicide formation provides the advantages of low ohmic contacts.

In order to complete the contact formation, a contact metal 148 such asCu or W is deposited to fill the contact holes, as further illustratedin FIG. 1N. These materials are intended to be illustrative and notlimiting. The scope of the invention is intended to extend to anycontact materials conventionally used or proposed in the future. Asillustrated in FIG. 1P, a CMP step planarizes the top surface of thedevice.

Although the described method does not perform a self-aligned implant ofthe source and drain regions, alignment problems can be effectivelycontrolled by preferably restricting alignment in one of two directions.That is, alignment concerns can be limited to only one direction sincethe critical dimensions for gate electrodes refer to the width of thegate.

The damascene methods for forming the gate and gate dielectric filmenable the formation of an epitaxial silicon layer for the channelregion of the transistor. That is, according to a second embodiment,rather than stopping the trench etch on the silicon substrate as in thefirst embodiment, the trench etch is extended partially into the siliconsubstrate. The etched trench extension into the substrate, i.e., thechannel etch, is then filled with epitaxial silicon by a depositiontechnique, for example, by chemical vapor deposition methods. Followingthe growth of the epitaxial silicon portion, the trench is lined with athin high-k gate dielectric film followed by deposition of the gateconductor material, as described above in the first embodiment. Thisembodiment thus provides a transistor capable of higher performance dueto the formation of the inversion channel in the epitaxial siliconportion. In the second embodiment, the implanted epitaxial silicon isimplanted to form strained silicon in the channel. The strained Si canbe integrated onto Ge or SiGe. By creating the gate electrode and high-kdielectric film by this additive process, advanced characteristics canbe obtained suitable for the next generations for CMOS architectures.

FIGS. 2A-2G are diagrams illustrating a method of forming asemiconductor integrated circuit in accordance with a second embodimentof the present invention. This embodiment describes a process flowincluding an epitaxial grown channel portion. The steps illustrated inFIGS. 2A to 2G may alternatively be integrated into the process flowdescribed and illustrated in FIGS. 1A to 1N, preferably in lieu of FIGS.1F to 1J. That is, after definition of the source/drain implantsillustrated in FIG. 1E, the process flow proceeds to the gate electrodetrench etch illustrated in FIG. 2A. Once the gate electrode inaccordance with the second embodiment is formed, contact hole andcontact formation proceeds as illustrated in FIGS. 1K to 1N.

Initially, as illustrated in FIG. 2A, the first ILD layer 132 is formedon the substrate 102 for subsequent patterning and etching. Asillustrated in FIG. 2B, the gate electrode trench is defined in thefirst ILD layer 132 as described above with reference to FIG. 1G. Ratherthan stopping on the surface of the substrate 102 as described in thefirst embodiment, the etching continues into the substrate 102 to etch achannel 202 into the substrate, as illustrated in FIG. 2C. The depth ofthe channel etch can vary in accordance to the design but preferably isa sufficient depth such that the entire device inversion channel formsin the subsequently epitaxially grown region.

Next, as illustrated in FIG. 2D, epitaxial growth of the device channel204 occurs. The epitaxially grown channel 204 may be grown as strainedSi on Ge or on Si—Ge. Strained silicon is achieved by incorporating Gein the Silicon lattice. A primary advantage is controlling thecharacteristics of the channel with more precision. Impurities may beadded to modify the conductivity or stress of the channel to achievedifferent modes of operation for the transistor.

In essence, this embodiment enables the rebuilding of a pure channel tomeet the demanding requirement of future device technologies. Due to thelimitations of the base Si substrate material, particularly in terms ofcarrier mobility and intrinsic performance, efforts have been directedto substituting other materials for conventional silicon substrate.Strained Si technology enables improvements in CMOS performance andfunctionality through replacement conventional Si substrate with abiaxially strained thin Si film at the surface. The strained Si film haselectrical properties superior to bulk Si. For example, thesecharacteristics include greater electron and hole mobilities. Silicon inits strained state provides greater drive current capabilities for NMOSand PMOS transistors.

Following formation of the epitaxially grown channel 204, deposition ofthe high-k gate dielectric 206 occurs (See FIG. 2E), again in accordancewith the techniques and parameters described in the first embodimentwith respect to gate dielectric 134. Next, a gate electrode conductivematerial 208 is deposited, preferably comprising polysilicon ortungsten, as illustrated in FIG. 2F. Additional specific candidatesinclude Cu, W or Al as described earlier. This technique provides achoice of materials for the gate electrode. The process steps andparameters for depositing this gate conductive layer conforms to themethods of forming the gate electrode conductive layer 136 described andillustrated in FIG. 1I.

After deposition of the gate electrode conductive layer 208, chemicalmechanical polishing is preferably performed to remove the overburdenregion and thus to planarize the gate electrode 208 to be coplanar withthe top surface of the dielectric layer 208. The partially formed deviceafter completion of the planarization step is illustrated in FIG. 2G.Formation of the contact holes and contacts then proceeds in accordancewith the process steps illustrated and described in the first embodimentwith reference to FIGS. 1K to 1N.

The present invention overcomes problems in the formation of gateelectrodes and high-k gate dielectric films in ultra submicron processtechnologies. The novel sequencing provided in embodiments of thepresent invention form the high-k dielectric film and the gate electrodeafter the high temperature anneal processes have been completed. Lightlydoped diffusion (LDD) regions are then formed in surface regions of thesubstrate. In conventional processes, they are self-aligned with thestructure of the gate electrode, owing to the prior formation andpatterning to the gate. The surfaces of the source drain regions and thegate electrode are then salicided to improve contact resistance. Sincethe salicides are formed after contact etch, improvements in deviceperformance result form reduced transistor leakage. Specifically, thelack of salicide near the shallow trench isolation recess preventsrelated transistor leakage due to the salicide crossing the bentjunction in these regions.

Although the foregoing invention has been described in some detail forpurposes of clarity of understanding, it will be apparent that certainchanges and modifications may be practiced within the scope of theappended claims. Accordingly, the present embodiments are to beconsidered as illustrative and not restrictive, and the invention is notto be limited to the details given herein, but may be modified withinthe scope and equivalents of the appended claims.

1. A method of forming an integrated circuit transistor comprising:depositing a first dielectric layer on a substrate; etching a gateelectrode trench in the first dielectric layer; depositing a conformalgate dielectric film to line the trench; and depositing a gate electrodeconductor in the trench to cover the gate dielectric film and fill thetrench.
 2. The method as recited in claim 1 wherein the gate electrodetrench etch stops on the underlying substrate.
 3. The method as recitedin claim 1 wherein the gate electrode trench is extended such that thebottom of the trench forms a depression in the substrate.
 4. The methodas recited in claim 1 wherein the first dielectric layer comprises oneof undoped silicate glass and phospho-silicate glass.
 5. The method asrecited in claim 1 wherein the gate electrode conductor comprisesaluminum.
 6. The method as recited in claim 1 wherein the gate electrodeconductor comprises one of aluminum, tungsten, and polysilicon.
 7. Themethod as recited in claim 1 further comprising defining a drain andsource region in the substrate before depositing the first dielectriclayer on the substrate.
 8. The method as recited in claim 7 furthercomprising defining a lightly doped drain region and a punch throughimplant stop layer in the substrate before depositing the firstdielectric layer on the substrate.
 9. The method as recited in claim 1further comprising defining a lightly doped drain region and a punchthrough implant stop layer in the substrate before depositing the firstdielectric layer on the substrate.
 10. The method as recited in claim 1wherein the first dielectric layer is an interlayer dielectric andfurther comprising forming at least one contact hole in the firstinterlayer dielectric.
 11. The method as recited in claim 10 wherein theat least one contact hole exposes at least one of a source, a drain, ora gate electrode and further comprising forming a salicide on theexposed at least one of a source, a drain, and a gate electrode.
 12. Themethod as recited in claim 1 further comprising etching a channel trenchinto the substrate beneath the gate electrode trench and epitaxiallygrowing a silicon layer in the channel trench.
 13. The method as recitedin claim 12 wherein the epitaxially grown silicon layer is a strainedsilicon layer formed on a SiGe layer grown in the channel trench. 14.The method as recited in claim 12 wherein the epitaxially grown siliconlayer is a strained silicon layer formed on a Ge layer grown in thechannel trench.
 15. The method as recited in claim 14 wherein thestrained silicon substrate implant is formed on one of a SiGe or Gelayer.
 16. A method of forming a semiconductor integrated circuit, themethod comprising: forming a source and drain diffusion region on asemiconductor substrate; forming an interlayer dielectric layer on thesemiconductor substrate after formation of the source and draindiffusions; etching a gate electrode trench in the interlayer dielectriclayer, the gate electrode trench configured for the placement of a gateelectrode to control the current between the source and drain regions;lining the gate electrode trench with a gate dielectric layer; anddepositing a gate electrode conductive material in the gate electrodetrench after lining the trench with the gate dielectric film.
 17. Themethod as recited in claim 16 wherein the gate electrode trench etchstops on the substrate.